1. Field of the Invention
The present invention relates to a method of fabricating a metal interconnection of semiconductor device and, more particularly, to a method of forming a metal interconnection by using a bottom metal layer as a seed layer instead of using a physical seed as an electrode.
2. Background of the Related Art
FIGS. 1a through 1c illustrate, in cross-sectional views, the process steps for forming a metal interconnection of semiconductor device having a line damascene structure according to a prior art. The line damascene structure is made through forming a trench with an adequate depth on an insulating layer in the form of a line and forming a metal layer in the trench.
Referring to FIG. 1a, a line-shaped trench is formed on an insulating layer 10 deposited on a substrate (not shown) using photolithography. A diffusion barrier layer 12 is deposited over the surface of the insulating layer including the trench. Then, a seed layer 14 is formed through depositing copper on the diffusion barrier layer 12 using physical vapor deposition (hereinafter referred to as “PVD”) such as sputtering.
Referring to FIG. 1b, a copper plating layer 16 is formed on the seed layer 14 by an electroplating method. Here, the plating layer 16 is formed thick such that the trench is filled completely.
Referring to FIG. 1c, the plating layer 16 is etched by chemical mechanical polishing (hereinafter referred to as “CMP”) until the insulating layer is exposed. Thus, the diffusion barrier layer 12, the seed layer 14, and the plating layer 16 remain only in the trench 11 to complete a metal interconnection 16a. 
As another prior art, there is a dual-damascene structure. FIGS. 2a through 2d illustrate a method for forming a metal interconnection having the dual-damascene structure according to a prior art.
Referring to FIG. 2a, a bottom conducting layer 28 is formed on a substrate (not shown) at regular intervals. Then an insulating layer is deposited over the bottom conducting layer, and a metal layer 26a is formed at regular intervals. The bottom conducting layer 28 is electrically connected with the metal layer 26a through a contact hole area 30. FIGS. 2b through 2d show, in cross-sectional views of FIG. 2a taken along a line VII–VII′, the process steps for forming a metal interconnection with the dual-damascene structure.
Referring to FIG. 2b, a conducting material is deposited and patterned on a substrate (not shown) to form a bottom conducting layer 28. An insulating layer 20 is deposited over the bottom conducting layer 28, and a contact hole area 30 and a trench area coupled to the contact hole area 30 are formed by means of photolithography. Then, a diffusion barrier layer 22 and a seed layer 24 are formed in sequence over the substrate including the contact hole area and the trench area.
Referring to FIG. 2c, the substrate with the seed layer 24 is loaded in an electroplating apparatus and, then, a copper plating layer 26 is formed by electroplating. A surface planarization process is performed for the substrate with the plating layer using CMP. The surface planarization is performed for the plating layer 26, the seed layer 24, and the diffusion barrier layer 22 until the surface of the insulating layer 20 is exposed to form a metal interconnection 26a with a dual-damascene structure.
However, the above-mentioned methods of forming a metal interconnection cause several problems as follows. First, while removing the copper layer using the CMP, the insulating layer is eroded due to density difference in the metal layer pattern, thereby causing badness of product. Second, if the seed layer and the diffusion barrier layer have a different polishing speed respectively, the seed layer and the diffusion barrier layer has to be respectively polished using a different slurry, thereby complicating the CMP process and increasing production cost. Third, in the copper electroplating, the copper layer is grown on the equipotential surface of the seed layer by contacting an electrode to the seed layer. Here, if the seed layer is not formed in a narrow and deep hole, the copper may be not deposited uniformly on the seed layer to form void 32 and 32a. Thus, the semiconductor device may not work due to a short circuit. Forth, if there are particles on the diffusion barrier layer or the seed layer, the copper layer cannot be formed on the equipotential surface of the seed layer in electroplating and an area without copper can be formed, thereby causing a short circuit.
Finally, in electroplating, the copper film grows simultaneously on the bottom and the lateral walls of the hole, as shown in FIG. 3. Therefore, such a mixing in growth direction of copper causes electro-migration, stress-migration, and so on, thereby having a bad effect on device reliability.